`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	forward(
    input	    [63:0]		Rs1_idu,
    input	    [63:0]		Rs2_idu,

    input	    [63:0]		Rd_lsu,   
    input	    [63:0]		Rd_wbu,

    input       [1: 0]      forward_1,
    input       [1: 0]      forward_2,

    output reg  [63:0]      Rs1_exu,
    output reg  [63:0]      Rs2_exu
);  parameter zero = 63'd0;
    always@(*)begin
        case(forward_1)
            2'b00:
                Rs1_exu = Rs1_idu;
            2'b01:
                Rs1_exu = Rd_lsu;
            2'b10:
                Rs1_exu = Rd_wbu;
            default:
                Rs1_exu = zero;
        endcase
    end
    always@(*)begin
        case(forward_2)
            2'b00:
                Rs2_exu = Rs2_idu;
            2'b01:
                Rs2_exu = Rd_lsu;
            2'b10:
                Rs2_exu = Rd_wbu;
            default:
                Rs2_exu = zero;
        endcase
    end

endmodule